Call For Presentations & Posters for TestConX 2019
March 3 - 6, 2019
Hilton Phoenix / Mesa Hotel - Mesa, Arizona

The Burn-in and Test Strategies (BiTS) Workshop is seeking presentation and poster proposals on a broad range of test and burn-in topics.

Each presentation at BiTS is provided a thirty minute presentation slot (approximately 25 minutes for the prsesentation with 5 minutes for questions and answers). Authors only neeed to prepare a PowerPoint presentation. (There is no paper to write.)

Posters are three oversized 24" W x 36" H pages which are displayed during an interactive session with the attendees.

Presentations and Poster final submissions are due in mid-January.

Abstracts submitted by October 1, 2018 will receive a $25 Starbucks Gift Card (or equivalent) and be eligible for the Early Bird Prize drawing* if accepted and presented at TestConX 2019.

Please submit a 250 to 500 word abstract for presentations or posters of your original, previously unpublished, technical presentation by October 31, 2018.

Submit via:
  • Online form
  • Email to [javascript protected email address] including title of presentation, complete contact information (name, affiliation/company name, job title, email address, phone number, and mailing address) for each author, and name of presenter.

Abstracts will be reviewed and authors will be notified around November 16, 2018.

Topics of interest include, but are not limited to:

Device Specific Testing
Test engineering perspective on testing:
  • Power Amplifiers
  • Power Management ICs
  • Networking IC's
  • RF Front End Modules
  • A/D converters
  • Microcontrollers
  • Sensors
  • Ultra-high reliability
  • Medical
Testing Advanced Packaging Technologies
  • Heterogeneous Integration (HI) and FanOut Wafer Level Packaging (FOWLP) testing
  • PoP, Bare Die, system on a chip (SOC), and 3D package testing
  • Wafer level chip scale (WLCSP) test for Known Good Die (KGD) or final test
  • Minimizing metals & plating of material test challenges
  • Low power and/or alternative power testing
  • Lead-Free test challenges
  • Reducing/recycling materials used in shipping sockets, PCBs and other products
  • Interconnect solutions for photovoltaic products
PCB Design & Manufacturing Challenges
Printed Circuit Board (PCB) challenges for Test & Burn-in:
  • High temperature burn-in board applications
  • High data rate test applications
  • Space Transformers
  • Ultra-fine pitch
  • Board to Board Interconnects
  • CTE, force & planarity issues
  • Materials & construction for Temperature/Humidity/Bias (THB), highly accelerated stress test (HAST) or other special applications
Market Focused Testing
Automotive electronics
  • Accelerometers
  • Pressure sensors
  • Radar
  • Communications
Internet of Things (IOT)
  • RF
  • Microcontrollers
  • Sensors
  • Memory
  • System level
  • Machine to machine (MTM)
  • cellular 5G
  • WLAN 802.11ad (60GHz)
  • Radar (77GHz)
  • Backhaul (20-90GHz)
Printed Electronics
Test Cell, Test Process & Operational Challenges
  • Test Cell Integration
  • Test & Burn-in floor operations
  • Cross-functional up- & down-stream challenges with wafer sort, quality, packaging organizations etc.
  • Socket repair, cleaning, and re-plating methods
  • Value Engineering: methods and techniques for reducing cost of ownership, achieving low-cost test, burn-in, etc.
  • Massively parallel and non-singulated test
  • Strategies for reducing qualification and production time
  • Socket & PCB verification, checkout & qualification
  • Module or System Level Test (SLT) to enhance or replace Final Test
  • Panel processing, handling, and testing
  • Strip Testing, and Test-in-Tray
  • Very high insertion / extraction cycles
  • Automation environment requirements
  • High reliability testing for mission critical and medical applications
  • Microelectromechanical system (MEMS) and non-electrical (optical, fluidic, magnetic, acoustic, etc.) stimuli testing
  • Cradle to cradle manufacturing
  • Factory automation
  • Final test and wafer probe convergence
Electrical, Mechanical, & Thermal Test Challenges
  • Wafer Level Packages, Thinner Packages & Package-on-Package (PoP)
  • Design tools: geometric dimensioning and tolerancing (GD&T); finite element analysis (FEA), etc.
  • Ball deformation & package stress
  • Package alignment
  • High frequency and high data rate techniques and technologies
  • High current, high power, and/or high temperature device testing
  • Handler & change kit designs and considerations
  • Managing electro-static discharge (ESD)
  • Fine Pitch Kelvin Contacting
  • Thermal management and modeling
  • Contact technology: dissimilar metal interface degradation, carbon nanotube developments, non-traditional interface materials, contact reliability in test and burn-in conditions
  • Voltage and current extremes, high and low
  • Socket thermal expansion (CTE), force & planarity issues
  • Ultra-fine pitch interconnects (0.25 mm and smaller)
Validation, Bring-Up, & System Level Test
  • Initial silicon bring-up and validation
  • System level validation / characterization testing
  • Automation & integration challenges
  • Zero keep-out zone sockets
  • Thermal control & thermal margining
  • Strategies for quick turn, low volume & low cost hardware and sockets
  • Scaling and automation to move from lab to high volume production
Advanced Contacting Technologies
  • Board to Board Interconnects
  • Ultra-fine pitch Interconnects (0.25 mm and smaller)
  • Wafer level chip scale (WLCSP) test for Known Good Die (KGD) or final test
  • Flexible circuit technology and interconnect to rigid PCB

Advanced Materials for Test & Burn-in
  • Nano sciences (carbon nanotube) and technology materials
  • Energy conversion and storage materials
  • Semiconductor and electronics materials and devices
  • Organic materials and thin film technology
  • Pb-free electronic materials
  • Dissimilar metal interface degradation
  • Emerging Electronics – mobile and bio-implantable materials, TSVs for 3Ds, MEMS, etc.
  • Materials for Temperature/Humidity/Bias (THB), highly accelerated stress test (HAST) or other special applications
  • 3D printing of sockets and test hardware

As an Author you’ll contribute to a stimulating and comprehensive technical program by sharing your latest work and advancements with colleagues from around the globe. Whether you’ve previously made a podium or poster presentation at BiTS, or are considering becoming an author for the first time, we encourage and welcome you to submit an abstract for your proposed presentation or poster.

BiTS is the world’s premier event for what is Now & Next in test and burn-in of packaged integrated circuits (ICs), dedicated to providing a forum for the latest information on a broad range of topics related to burn-in and test. The BiTS Workshop is the place where industry colleagues from around the world come to learn from presentations made by people like you.

For additional questions and other inquiries please contact:

[javascript protected email address]

* Void where prohibited by law or company policy.

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