TestConX 2019

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Monday March 4, 2019

7:00 a

Continental Breakfast

Start the day right and enjoy the continental breakfast while networking with other attendees.

8:30 a

Welcome
Red Mountain Ballroom
Opening Remarks

Welcoming remarks from the General Chair, Ira Feldman

9:00 a

Kenote
Red Mountain Ballroom
Keynote
 
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Michael Campbell
Senior Vice President of Engineering
QUALCOMM CDMA Technologies

Title and abstract to be announced

 
 

Keynote sponsored by Indium Corporation Indium Logo

10:00 a

Break & Networking

Enjoy the break and networking time.

10:30 a

Session 1A
Red Mountain Ballroom 1 & 2
QAM and Get It!
High Frequency (HF), 5G, and millimeter-wave (mm-wave)

Recent trends in the explosive growth of wireless data traffic makes millimeter wave (mmWave) communication the most attractive solution to this challenge in the next generation of “5G” mobile communication systems. Millimeter wave is an undeveloped band of the radio spectrum that can be used in a broad range of products and services like high speed, point-to-point wireless local area networks (WLANs), and broadband access. Millimeter wave is attractive for a variety of services on mobile and wireless networks, as it allows for faster than existing data rates up to 10 Gbps. Testing these high data rate brings unique challenges. The first presentation addresses these challenges by utilizing a hybrid cantilever and pogo technology to enable the shortest impedance controlled path from the tester to the device under test (DUT). Then the high speed problem is attacked via modeling and simulation in the second presentation. The effect of small changes in device location and its impact on key electrical performance criteria is examined in detail. AIP (Antenna in Package) is the new trend in IC packaging to support mmWave with the next presentation reviewing how to implement and test AIPs over the air test. The last presentation will expand on the challenges of over the air test with issues such as power amplifier efficiency, receiver sensitivity due to thermal changes, and more.

“Solution for mmWave Wafer Probe Applications and Field Results”
Jason Mroczkowski
Cohu
“Testing of High Frequency 5G Applications and Why Simulation is Critical to Success”
Jeff Sherry
Johnstech International
Noureen Sajid
Johnstech International
Mark Appelquist
Johnstech International
“Over the Air Test for Antenna in Package IC”
Aaren Lonks
Cohu
Dongmei Han
Cohu
“RF Module Test Challenges”
Roger McAleenan
Advantest
Keith Schaub
Advantest
Ira Leventhal
Advantest

10:30 a

Session 1B
Red Mountain Ballroom 3
On the Bus
Advanced bus protocols for validation

Post-silicon validation takes place between initial silicon power on (PO) and product launch. The main goal of validation is to verify product functionality against the Engineering Design Specification. The session starts with an introduction of the benefits of a new industry specification that is being developed by the members of the MIPI Alliance’s Debug work group around using the MIPI I3C (an improved I2C) interface for debug and test that can communicate between the different components in systems/platforms. In the second presentation, an introduction to the MIPI SneakPeek Debug Protocol supporting low-bandwidth interfaces (TinySPP) will be given. The presentation will show the differences between the TinySPP and FullSPP. The goal for the participant is to learn about the TinySPP Debug protocol and understand how it can be used in either a hardware or software implementation. In the third presentation, timing issues on I3C interface and multiple strategies for coping with them in instrumentation and platform design will be addressed. In the final presentation, an innovative and scalable architecture developed for high performance mid-bus probing for PCIe 4.0, 5.0 and beyond will be covered.

“MIPI I3C: A New Bare-Metal Interface for Debug and Test”
Enrico Carrieri
Intel Corporation
“MIPI Tiny SneakPeek: An Optimized Debug Protocol for efficient Platform Debug”
Rolf Kühnis
Intel
“Coping with Latency in I3C”
Brad Smith
Intel
“A Scalable High Performance Mid-Bus Probing Solution for PCIe 4.0, 5.0, and Beyond”
Xiao-Ming Gao
Intel Corporation

12:30 p

Lunch

Lunch is served. Enjoy the break and networking time.

1:30 p

Session 2A
Red Mountain Ballroom 1 & 2
Wrap This Up?
Advanced Technology Packaging

Next-generation applications have continued to push advanced packaging technologies to achieve the required product performance. Wafer-level packaging, panel-level packaging, bumping, redistribution layers, fan out, and through-silicon vias are among the latest packaging technology becoming common as these new end applications grow in volume. Packaging will continue to explode with innovation and complexity to deliver the small-form-factor devices with powerful, high-speed functionality that consumers expect in next generation mobile electronics, healthcare, and other devices. This session begins with the challenges of testing biochips and biochemical microfluidic chips. Test procedure demands injecting different kinds of fluids on the sensor area for detecting and reaction during wafer probing under various temperature. The second presentation addresses the challenges of testing devices in frame/panel. These challenges include high coefficient of thermal expansion (CTE), local flexibility, and non-uniform heat distribution due to spaces in between devices. Lastly, contactor failure due to imbalance in the current distribution between multiple power and ground pins is presented. And the surprise is that a good contactor fails quicker as it draws more current in comparison to its out of specification neighbor with high contact resistance. An innovative current balancing technique involving electrically isolated PCB pads with independent programming of force current is presented as the solution to this challenge.

“Discussions of Testing Challenges and Technologies of Probing Bio-MEMS Sensors for Mass Production”
Wendy Chen
KYEC
Kuang-Hsiang Liu
KYEC
Chieh-Wen Lu
KYEC
Hsi-Hua Chou
KYEC
Po-Ting Lai
KYEC
Yu-Hao Ciou
KYEC
“Reliability Testing of Panels and Strips”
Carl Kasinski
Aehr Test Systems
“Current Balancing Technique”
Rodolfo "Jock" Sta Maria, Jr.
Texas instruments
Thiha Shwe
Texas Instruments
“Metal Oxide (MOX) Gas Sensor Testing”
Dale Johnson
Marvin Test Solutions

1:30 p

Session 2B
Red Mountain Ballroom 3
Measuring Up
Validation Measurements and Techniques

This session focusses on validation issues and techniques used in solving these challenges. Use of an innovative and custom interposer for validating high-speed LPDDR4 memory interface for package-on-package devices that also reduces motherboard design complexity will be presented first. The second presentation, will explore the potential of using a non-linear passive devices for accurate current measurements. This is critical to creation of a system with efficient power regulation for maximum battery life. Environmental stress tests are necessary tests to assess early package moisture sensitivity levels. In the third presenter will cover case studies on the environmental stress issues and fails. In the last presentation, a new digital transformation solution known as Virtual Validation Farm (V2F) will be discussed to enable OEMs to have first access to A0 silicon debug to accelerate Time-to-Market (TTM) for a new product.

“Validating LPDDR4x memory in a Package-on-Package (PoP) architecture using a ball grid array (BGA) interposer”
Estanislao Aguayo
Intel
Matthew Priolo
Intel
Bernard Tam
Intel
“System current measurement using non-linear passive device”
Thomas Bowns
Intel Corporation
“Package Level Environmental Stress Fails and Studies”
Krishna Mohan Chavali
Globalfoundries US Inc
“Time-to-Market Acceleration with Virtual Validation Farm in Post-Silicon”
Seong Guan Ooi
Intel Corporation
Angie See Tien "Angie" Ng
Intel Corporation

3:30 p

Poster Session
Red Mountain Foyer
Poster Session
Break & Networking

Poster Sessions are a great way to network through interaction with the poster presenters and other curious bystanders. At the same time enjoy the break refeshments and networking.

“Design and Analysis of 3D MEMS Co-axial Structure”
Tae-Kyun "TK" Kim
Microfriend Inc.
YongHo Cho
Microfriend Inc.
Jongmyeon Lee
Microfriend Inc.
Shinkwon Han
Microfriend Inc.
“Spring probe pin design good for -1 db @ 60 Ghz and far beyond”
Hyungjun "AJ" Park
IWIN Co., Ltd.
“Stamped spring probe pins and Coax socket manufacturing at low cost”
Sang Yang "Samuel" Pak
IWIN Co., Ltd
“Innovative Test Contactor Cleaning Devices Developed for Floating Base Sockets”
Bret Humphrey
International Test Solutions
Jerry Broz
International Test Solutions
“Mechanical Reliability Enhancement of Ceramics for A High Parallelism Probe Card”
Sang-Gu Kang
Samsung Electronics
Sehoon Park
Samsung Electronics
Gyu-Yeol Kim
Samsung Electronics
Sang-Kyu Yoo
Samsung Electronics
“Coaxial Socket in mmWave Applications”
Collins Sun
WinWay Technology Co., Ltd.
Ryan Chen
WinWay Technology Co., Ltd.
Hayden Chen
WinWay Technology Co., Ltd.
“Testing of 80 GHz QFN Packages With Waveguide Interfaces”
Jeff Sherry
Johnstech International

4:30 p

Session 3A
Red Mountain Ballroom 1 & 2
Wring This Out
System Level Test

System level test (SLT) approaches test from a holistic level by using the device to test itself while often emulating actual customer usage. This is a drastic departure from traditional functional test which is typically targeted at testing for specific manufacturing defects and sensitivies . SLT requires the device under test (DUT) be placed in a socket on an application board that often uses the actual firmware, drivers, and operating system to test the DUT. The end result is an attempt to achieve a higher level of fault coverage in by using actual product hardware and software configurations. As each DUT requires its own hardware and software, standardization is a challenge. The first presenter will discuss how to mitigate this challenge and achieve common platforms. A unique view of how SLT and Burn-in fit together and can co-exist or overlap is discussed second. Lastly the challeges of 100% SLT at production as unit volume starts ramping is presented.

“SLT Test Fundamentals and Challenges”
John Yi
AMD
“A Holistic Approach to Test Coverage Across Final Test, Burn in and SLT”
Karthik Ranganathan
Astronics
“Trends in System Level Test”
Geeta Athalye
Teradyne Inc

4:30 p

Session 3B
Red Mountain Ballroom 3
Breaking It!
Validation & Characterization

Validation and/or debug of new products by conducting different stress/environmental tests and developing different debug techniques is the focus of this session. Case studies on the functional stress failures that are encountered by conducting different environmental tests that are done as part of fab processing or a new product’s assembly packaging qualification flow will be presented first. The second presentor will show the evolution of the debug solutions in mobile systems addressed by MIPI and the USB organization. Lastly, an introduction of the different debug standards used for closed-chassis debug and to see how they create a complete solution will be discussed.

“Functional Stress Failures and Case Studies on HVS, Burn-In and ESD/EOS Stresses”
Krishna Mohan Chavali
Globalfoundries US Inc
“Standardized Closed-Chassis Debug Solution for Platform and System Debug”
Rolf Kühnis
Intel

6:00 p

TestConX EXPO & Reception

The TestConX EXPO is a very popular part of the TestConX program with many great exhibits for connecting electronic test professionals to solutions. There is always something new to see or someone new to meet. Not to mention excellent food, drinks, and time for attendees to network with exhibitors!

9:00 p

Adjourn

Program subject to change without notice.