BiTS 2018

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Tuesday March 6, 2018

7:00 a

Continental Breakfast

Start the day right and enjoy the continental breakfast while networking with other attendees.

8:00 a

Distinguished Speaker
Red Mountain Ballroom
Distinguished Speaker
“The Long Road to Energy Efficiency”
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Barnes Cooper
Intel Fellow
Client Computing Group
Chief Architect, Power Management and Energy Efficiency
Intel Corporation

This talk will provide a factual (and hopefully entertaining) look at the evolution of modern power management techniques and mechanisms. It will highlight breakthroughs in power management technology over time. PCs have progressed in energy efficiency not just in small changes year of year, but rather in a series of significant realizations that turned into fundamental revolutionary changes to that status quo, which have become fundamental to all modern battery-powered computing devices. We will cover the basic infrastructure in the first mobile PCs through the contemporary approaches that are in play in devices today that provide integrated deep silicon and platform level coordinated power management working in conjunction with modern operating systems.

Along the way, we will illustrate the impacts by sharing real world data and projections of energy consumption across product categories, and it will highlight the power challenges to overcome as usage models become far more challenging (e.g. virtual-reality, artificial intelligence). Worldwide energy regulations and the near-term immediate impact to product will be reviewed. We will also discuss the manufacture, test, and printed circuit board design problems created as power targets and levels rapidly shrink year over year. A set of challenges to work through as an industry will conclude.

 

9:00 a

Session 4
Red Mountain Ballroom
Speedy Reflections
Electrical Simulation

In order to accurately predict the performance of the electronic devices before they are built,very careful electrical simulation is required. As data transfer rates of electronic devices increase, greater are the challenges to accurately simulate the electrical performance of the device under test (DUT). It is essential to very closely correlate the actual measured electrical data with the simulation results to improve overall accuracy. What impedance control means and the importance of a controlled impedance system for accurately obtaining test results of the DUT will be covered first. And the second presenter will discuss 3D electro-magnetic (EM) field simulation tools and how to accurately correlate simulation results to the actual measured data.

“Application of Uncertainty Quantification in RF Simulations of Test Socket”
Noah Weichselbaum
Smiths Interconnect
Jiachun "Frank" Zhou
Smiths Intercconect
Resty Querubin
Smiths Intercconect
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“Impedance Controlled Contacts in the Test System”
Noureen Sajid
Johnstech International
Jeff Sherry
Johnstech International
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10:00 a

Poster Session 2
Red Mountain Foyer
Poster Session
Break & Networking

Poster Sessions are a great way to network through interaction with the poster presenters and other curious bystanders. At the same time enjoy the break refeshments and networking.

“Co-Axial Contacting”
James "Jim" Brandes
Xcerra
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“Characterization of Electronic Cooling Solution & Thermal Interface Material using Thermal Test Vehicle”
Suhail Azim
Test Tooling Solutions Group
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“Active Load Board Thermal Control”
Nathan Hogg
Texas Instruments
Marshall Worrall
Texas Instruments
Nathan Verges
Sensata Technologies
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“Innovative Ground Block Pin Design for Improved High-Frequency Test Performance over a Conventional Ground Block Approach”
Eichi "Osato" Osato
Micronics Japan Company
Soheil Khavandi
MJC
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“Printed Circuit Board Via Technology Limitations and Optimization”
Estanislao Aguayo
Intel
Vothy Heang
Intel
Christopher Kinney
Intel
Matthew Priolo
Intel
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“An Innovative Vertical Probing System for High Speed/Frequency Applications”
Pang Cheng "Oliver" Chiu
Jthink Technology
Duncan Huang
Jthink Technology
Sung-Mao Wu
National University of Kaohsiung
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“A new methodology to improve power integrity of high parallelism probe card”
Min-Seok "Bryan" Lee
Samsung Electronics
Gyu Yeol Kim
Samsung Electronics
Sang Kyu Yoo
Samsung Electronics
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“Coaxial IC Socket for PAM4 & High Power Specification Requirement”
Tatsumi "Watabe" Watabe
S.E.R. Corporation
Makoto Kawamura
S.E.R. Corporation
Hiroyuki Yamakoshi
S.E.R. Corporation
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“Spring probe with reliable signal path and low cost for high speed/high pin count socket”
Sang Yang "Samuel" Pak
IWIN
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“Low cost/High performance one piece spring probe pins for Burn-in test”
Hyungjun "AJ" Park
IWIN Co., Ltd
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“Current Carrying Capability Limitations and Adaptions to New Requirements for Contact Springs”
Stefan Engelbrecht
Cohu
Markus Wagner
Cohu
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“The Importance of Registration in PCB Manufacturing Processes”
Brandon Sherrieb
Integrated Test Corporation
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11:00 a

Session 5
Red Mountain Ballroom
Life Cycle Panel
Interactive Discussion

A dynamic panel session between suppliers and integrated device manufacturers (IDMs) on standardization methodology to define life cycle of socket technologies. Six panelists who are experts in their field will address this important topic moderated by two industry veterans. The audience can expect a classic debate between the supplier and IDMs regarding what life cycle really means, why there is so much variation and interpretation, what factors impact test methodology, and what ultimately contributes to the results from both perspectives. Bring your tough questions since audience participation is highly encouraged!

“Socket Supplier”
Jiachun "Frank" Zhou
Smiths Interconnect
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“Semiconductor Device Manufacturer”
Rahima Mohammed
Intel
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“Socket Supplier”
Yoinjun "YJ" Shi
TwinSolution Technology (Shanghai) Co., Ltd.
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“Semiconductor Device Manufacturer”
James "Mig" Migliaccio
Qorvo
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“Socket Supplier”
Valts Treibergs
Xcerra
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“Semiconductor Device Manufacturer”
James "Mr. T" Tong
Texas Instruments
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“Panel Moderators”
Jason Mroczkowski
Xcerra
Jeffrey "Jeff" Roehr
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12:30 p

Lunch

Lunch is served. Enjoy the break and networking time.

1:30 p

Session 6
Red Mountain Ballroom
Making Certain
Debug and Validation

Debug and validation both at the die-level and system-level insure that the system or end-product is designed within specification and will work as intended without any issues even in the presence of manufacturing variations. There are significant challenges in both bare die qualification and new product validation to make sure that the final product is free of any “bugs” before shipping it to the end customer. Innovative debug and validation methods and techniques will show how many of these challenges may be solved. At the bare-die level and system level, these methods presented include: how to reduce time for first silicon bring-up and volume validation, how to qualify bare die using both thermal simulations and actual hardware testing, how to use single-node systems to scale out validation and mimic the customer data center environment, and how to effectively debug low power system on a chip (SOC) devices.

“Path to First Boot and Volume Validation: Challenges and Opportunity”
Vikas Kumar
Intel
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“Thermal Performance of Burn-in Board for Bare Die Qualification”
Sujata Paul
Cisco Systems
Jason Cullen
Plastronics
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“At Scale Cluster Validation”
Antonio Villa
Intel
Victor Rodriguez Bahena
Intel
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“SOC Low Power Debug Techniques”
Krishna Dandamaraju
Intel Corporation
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3:30 p

BiTS EXPO

Continue to explore the great exhibits at the BiTS EXPO to see what is Now & Next in the test and burn-in of packaged semiconductors. There is always something new to see or someone new to meet. Refreshments and drinks are served but don't spoil your appetite before the BiTS Social...

6:30 p

BiTS Social Event

Continue the networking with your colleagues and industry friends at the BiTS Social Event.

Regardless of the theme (to be announced) there is lots of fun and great food in store!

9:30 p

Adjourn

Program subject to change without notice.