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Tuesday March 6, 2018
Start the day right and enjoy the continental breakfast while networking with other attendees.
Client Computing Group
Chief Architect, Power Management and Energy Efficiency
To be announced
Barnes Cooper is an Intel Fellow and the chief architect for power management and energy efficiency in the Client Computing Group at Intel Corporation. He leads the development of PC power management technologies, a topic that has been the focus of his entire career.
Since joining Intel in 1995, Cooper has led the development of multiple power management technologies, including the foundational architecture of the original ACPI 1.0 specification; Intel® SpeedStep® technology; ACPI 2.0 extensions and the Intel architecture interface definition for multi-core and multithreaded power management states; a new converged platform power management framework known as Power Optimizer; and hardware duty cycling. He also led programs designed to enhance the energy efficiency of many PC I/O technologies, including USB, eDP and PCIe. Cooper has also collaborated with Microsoft on power management features, algorithms and energy efficiency optimizations since 1996 and continues to focus on key product transitions for Windows, such as the move to Modern Standby mode.
More recently, he has led efforts to meet stringent new energy standards calling for considerable desktop platform power reductions. He has also contributed to the development of many features related to power management, including cacheable system management mode memory, the Intel® Rapid Start technology and Battery Life Analyzer. During his Intel career, he has received five Intel Achievement Awards, the company's highest recognition. He has also been granted nearly 70 patents in the area of power management, with additional patents pending. Cooper earned a bachelor's degree in electrical engineering from the University of California, Irvine.
In order to accurately predict the performance of the electronic devices before they are built,very careful electrical simulation is required. As data transfer rates of electronic devices increase, greater are the challenges to accurately simulate the electrical performance of the device under test (DUT). It is essential to very closely correlate the actual measured electrical data with the simulation results to improve overall accuracy. What impedance control means and the importance of a controlled impedance system for accurately obtaining test results of the DUT will be covered first. And the second presenter will discuss 3D electro-magnetic (EM) field simulation tools and how to accurately correlate simulation results to the actual measured data.
Poster Sessions are a great way to network through interaction with the poster presenters and other curious bystanders. At the same time enjoy the break refeshments and networking.
A dynamic panel session between suppliers and integrated device manufacturers (IDMs) on standardization methodology to define life cycle of socket technologies. Six panelists who are experts in their field will address this important topic moderated by two industry veterans. The audience can expect a classic debate between the supplier and IDMs regarding what life cycle really means, why there is so much variation and interpretation, what factors impact test methodology, and what ultimately contributes to the results from both perspectives. Bring your tough questions since audience participation is highly encouraged!
Lunch is served. Enjoy the break and networking time.
Debug and validation both at the die-level and system-level insure that the system or end-product is designed within specification and will work as intended without any issues even in the presence of manufacturing variations. There are significant challenges in both bare die qualification and new product validation to make sure that the final product is free of any “bugs” before shipping it to the end customer. Innovative debug and validation methods and techniques will show how many of these challenges may be solved. At the bare-die level and system level, these methods presented include: how to reduce time for first silicon bring-up and volume validation, how to qualify bare die using both thermal simulations and actual hardware testing, how to use single-node systems to scale out validation and mimic the customer data center environment, and how to effectively debug low power system on a chip (SOC) devices.
Continue to explore the great exhibits at the BiTS EXPO to see what is Now & Next in the test and burn-in of packaged semiconductors. There is always something new to see or someone new to meet. Refreshments and drinks are served but don't spoil your appetite before the BiTS Social...
BiTS Social Event
Continue the networking with your colleagues and industry friends at the BiTS Social Event.
Regardless of the theme (to be announced) there is lots of fun and great food in store!
Program subject to change without notice.