BiTS China 2016 Advance Program

Join us for the second annual BiTS event in China!

BiTS China will be a one day event featuring technical presentations highlighting new regional presentations along with presentations from BiTS award winning authors. Learn what is Now & Next in test and burn-in of semiconductors!

There will be a BiTS EXPO featuring international and local suppliers. This combined with great food will provide excellent opportunities for networking.

Please see the detailed agenda below for this great event!

BiTS China 2016
Tuesday September 13, 2016
DoubleTree by Hilton Hotel Suzhou
275 Suzhou Avenue East Industrial Park, Suzhou, 215028, China
8:00 - 9:00
Please arrive early to check-in and pickup your conference badge and materials prior to the program start.
9:00 - 9:15
Opening Remarks
Welcoming remarks from
Ira Feldman, BiTS Workshop General Chair, and
Steven Zheng, BiTS China Chair
Link to Opening Remarks
9:15 - 10:00
Keynote Address
"Evolutions in Packaging Technologies for IoT – Assembly and Testing"
Yifan Guo
Yifan Guo
Vice President
Advanced Semiconductor Engineering (ASE)

"Evolutions in Packaging Technologies for IoT – Assembly and Testing"
"物联网封装革命- 组装与测试"
Yifan Guo 郭一凡
ASE Assembly and Test

As the IoT applications become a more and more important part of people’s life, packaging technologies are also evolved to meet the assembly and testing challenges for building the required semiconductor devices. In today’s world, as the rapid expansions of IoT applications, typically presented by the mobile/wearable devices and networks, consumer products are high volume and low cost, small and power efficient. These applications impose requirements for highly integrated system solutions and associated new assembly and testing technologies. The SiP (System in Package) is one of the emerging technology for an effective packaging solution. In this presentation, the evolutions of packaging technologies in the IoT era is introduces. The SiP technology, assembly and testing processes and challenges are presented. The potential future packaging technology requirements and developments for IoT are discussed.


Biography (English)

Yifan Guo

Yifan Guo is vice president of ASE Assembly and Test in Shanghai, ASE China. With over thirty years experience, he has performed roles in both academia and industry. He previously held positions as Professor and Adjunct Professor at Virginia Tech, State University of New York at Binghamton and University of California at Irvine. He has also worked for IBM, Motorola, Skyworks, ASE, in a variety of middle and high level management roles with responsibility for charges of R&D, engineering and operations. He holds nine patents and has published seven book chapters, and more than 50 refereed journal papers. Yifan Guo received his Ph.D degree from the Engineering Science and Mechanics (ESM) Department at Virginia Tech, and also holds an MBA from University of Redlands in California.

Biography (Chinese)



Link to Keynote Address


     -- Fifteen minute break --

10:15 - 12:15
Session 1
High Frequency & Burn-In
High frequency test and burn-in challenges
Regional and global experts will share their expertise and solutions to the challenges of high frequency test and burn-in.

Technical presentations in English or Chinese as noted. Slides in English with bilingual question & answer period.

"Implementation Challenges of an ATE Test Cell for At-Speed Production Test of 32 Gbps Applications"
"32 Gbps速度应用在自动测试单元量产实施中的挑战"
Jose Moreira
Hubert Werkmann
Daniel Lam
Bernhard Roth
Abstract and Biography (English)

This presentation will discuss the challenges of developing a production worthy ATE test cell using a standard ATE system for at-speed testing at data rates of 32 Gbps. We will discuss all the different aspects need for a production worthy and cost effective test cell including requirements on the standard ATE system, DUT test fixture and DUT socket design, calibration, mechanical integration, etc…

We will then present results from a real test cell already being used for volume production and also discuss the future of how this test cell can be augmented for future 56 Gbps/28 Gbaud applications.

Jose Moreira

Jose Moreira is a senior staff engineer in the test cell innovation team of the SOC business unit at Advantest Boeblingen, Germany. He has a master of science in electrical and computer engineering from the Technical University of Lisbon and he is a senior member of the IEEE and member of the DesignCon technical committee. Jose has published multiple papers in several conferences and received several best paper awards at DesignCon and VOICE. He also has multiple submitted and awarded patents. He is co-author of the book "Testing High-Speed Interfaces with Automated Test Equipment" published by Artech House.

Abstract and Biography (Chinese)

该文章主要讨论在ATE测试领域里32Gbps产品测试所面临的挑战,还将涉及量产的各方各面以及 高效使用ATE测试系统单元。如DUT的安装、socket设计、校准还有机械模块整合等。 我们将讨论一款在实际量产中已经应用的测试单元以及未来如何扩展到56Gbps/28 G带宽等更高领 域里应用。

Jose Moreira

Jose Moreira 为德国 Advantest Boeblingen 公司 SoC 事业部测试创新小组的高级工程师。他毕 业于里斯本技术大学电气和计算机工程系,获得理科硕士学位,也是 IEEE 的 DesignCon 技术 委员会会员高级会员。Jose 曾在多个技术会议中发表数篇论文,曾荣获 DesignCon and VOICE 最佳论文奖。他还持有多个技术专利,为 Artech House 出版的《测试高速接口自动化测试设 备【Testing High‐Speed Interfaces with Automated Test Equipment】》一书的联合署名作者。

Link to Session 1 Paper 1

"Addressing Challenges in High Temperature Burn-In"
Paolo Rodriguez
Analog Devices Philippines
Abstract and Biography (English)

The advent of distributed control systems in industries such as oil and gas exploration, avionics and automotive are requiring electronics to be in very close proximity to heat sources. Products in these applications are exposed to ambient temperatures above 150oC. Device reliability becomes a “critical” concern at this temperature range and must be addressed by performing rigorous product qualification testing. This paper presents the challenges and solutions employed in the development of a high temperature burn-in solution. The resulting burn-in oven system and associated hardware used during product qualification allowed High Temperature Operating Life (HTOL) to run at the maximum rated temperature of 210oC up to 2,000 hours. Components and materials used during the assembly of the oven and burn-in boards were carefully selected based on datasheet performance at high temperature. Most critical were the printed circuit board (PCB) used and the sockets mounted on the burn-in boards. Equally critical would be the oven connectors and backplane that serve as the electrical interface between the burn-in board and the oven drivers. Key design elements such as: a tower board rack allowed for uniform air circulation and temperature distribution; an innovative air curtain design that shield oven connectors from high temperature; double chamber wall construction and insulation that made sure that the heat was contained. These features ensured that this oven would be safe to operate, cost effective to maintain and be inherently more reliable that the high temperature integrated circuits it would qualify.

Paolo Rodriguez
Paolo joined Analog Devices Philippines in 2005 and is currently a product development engineer working on burn-in solutions for RF, Microwave and Video products. He started his career doing package and die level failure analysis before transitioning to Reliability where he worked on junction temperature measurement, device bias configurations and burn-in equipment qualification.

Abstract and Biography (Chinese)

由于分布式控制系统的出现,在石油、天然气勘探、航空电子设备和自动汽车等行业,常需 要电子元件无限接近热源。这些产品常暴露在150ºC的环境温度下使用。高温将成为元件可靠 性的一个重要指标,必须经历严格的产品测试。本文将专注于高温老化测试方案的挑战和方 法。预烧炉系统和相关的设备允许高温使用寿命(HTOL)达到210摄氏度2000小时。在烤箱和老 化板测试下的元器件和材料选择须谨慎考虑高温下的性能指标。大多数关键的印刷电路板使用 和测试插座安装在老化测试板上。同样地在老化测试板和烤箱驱动器之间的电接口也在烤箱 接口和基板起关键作用。 关键的设计部分,诸如:踏板架,须考虑到统一的空气循环和温度分布;一个创新的气幕设计,保护高温烤箱连接器;双腔体墙壁结构和绝缘结构以确保热量得到控制。 这些因素可以确保烤箱安全地操作,有效地维护成本和本质上提高高温集成电路设计的可靠性。

Paolo Rodriguez
Mr. Paolo 于2005年加入亚德诺半导体技术(菲律宾)有限公司, 目前是该公司的 产品研发工程师,负责老化测试应用高频、微波、及视频处理产品相关部分 。Mr.Paolo在转去做老化测试应用前的主要工作是封装和晶元级别失效分析,主攻 方向为结温,芯片偏置配置和老化设备验收工作。

Link to Session 1 Paper 2

"Derating Transient Voltage Suppressor Diodes for Burn-In Applications"
Gil Conanan
Analog Devices Philippines
Rolando Reyes
Analog Devices Philippines
Abstract and Biography (English)

It’s a tragic scenario when product engineers have high confidence on their products but customers ignore them because of doubts in quality due to failing test reports. Customers want high quality products. Burn-in test applications are not exempted from most discriminating perceptions to high quality products when weaknesses of protection circuits have not been cogitated. It is imperative to ensure high protection against set- up related failures to good devices during production run. Power failures, line noise and power fluctuations are set-up adversaries of good products.

Datasheet of protection diodes are often rated at 25° C but burn-in engineers need parameters at high temperature. Parameters such as peak power (Ppk) or Peak Current (Ipp) have derating curves readily available in most datasheets in the market. But deration of clamp voltage at 125° C is often missing, and is hypothetically estimated connoting high chances of error. From the test results of this research, a deration factor at high temperature is tested for longer duration to check its stability and robustness to high temperature and time. The actual behavior of clamp voltage at high temperature in this research should ensure that good products are not operating beyond absolute max rating even at transient events inside burn-in ovens.

Gil Conanan
Gil Conanan is a Junior Product Development Engineer at Analog Devices General Trias Inc Philippines. In 2014, he joined the Burn-in Engineering team. This team is responsible for developing new product burn-in capabilities and for sustaining of released products to improve and innovate the burn-in process. Gil also facilitates subcontractor qualifications and burn-in standardization for Analog Devices worldwide. He joined Analog Devices Inc. in 1997 as a line maintenance Technician. Then using his technical troubleshooting skills, he worked with the Electronics, Hardware PCB Debug and Design Group. Later he was promoted to his current position. He obtained his BS degree in Electronics and Communications Engineering from Manuel S. Enverga University, Lucena City, Philippines.

Abstract and Biography (Chinese)

工程师对自己的产品信心满满,客户却对产品质量嗤之以鼻 --这种悲剧情况时有发生,往往是因为测试报告结果失误。客户需要的是高品质的产品。很多时候对电路的保护没有充分考虑进去,使得老化测试却 在高品质高要求的产品面前备受冷眼,在量产时必须保证好的芯片免受相关失误故障的损害。如 电源 故障、电源波动以及线性噪声等都是好芯片被误判的罪魁祸首。

从数据表得到保护二极管正常工作时的温度在25° C,但是老化测试的工程师却需要更高温度时的 各项参数。像峰值功率或者峰值电流的derating曲线在市场上很多数据手册里的都是很容易找到的, 但如125° C时钳位电压的derating曲线却没有。如果刻意的假设又容易导致错误。经研究表明,一个 deration因子需要长时间持续的高温条件下的测量才可以确定其稳定性和真实性。高温条件下的钳位 电压真实行为时,也要确保对完好产品的操作不可以超过其最大额定功率,即便是在瞬态情况下。

Gil Conanan
Gil Conanan在菲律宾Analog Devices General Trias Inc担任初级产品开发工程师,他于2014年加入了老化测试工程团队,负责开发新产品老化工艺和维护已发布产品,改进和创新老化工艺。同时Gil也负责分包商认证、ADI全球老化标准化。他于1997年作为产线维护工程师加入ADI,而后基于其出色的调试维护能力,与电子硬件PCB调试与设计团队合作工作,升至目前职位。Gil毕业于菲律宾卢塞纳市曼努埃尔.S. Enverga大学电子与通信工程专业,取得学士学位。

Link to Session 1 Paper 3

"An Ignorable Testing Technology for High Speed/Frequency Device Testing"
Pang Cheng Chiu
Jthink Technology
Sung Mao Wu
National University of Kaohsiung
Lung Shu Huang
Jthink Technology
Kuan-I Cheng
National University of Kaohsiung
Chih-Cheng Chuang
National University of Kaohsiung
Abstract and Biography (English)

In traditional high speed, high frequency testing socket, signal pin is usually surrounded by one or more ground pins that defined by package ball name. Therefore, the impedance of signal pin is limited by the ball assignment of device under test(DUT). For example, one signal pin is surrounded by eight ground pins as an array, its impedance will be defined by the package ball pitch. Jthink Technology proposes an idea to design a metal socket to overcome this problem. With metal as socket housing, signal path can be regarded as a coaxial transmission line structure. Consequently, the pitch of this metal socket won’t be an issue regarding to impedance control.

On testing side, TRL calibration method can move calibration reference plane between pogo pin and load board. In this solution, the last mile of impedance matching is finished from ATE to DUT in high speed/frequency semiconductor testing.

To move the calibration reference plane to the tip of pogo pins, this study uses SOLT calibration method with open, short, load, through elements to have a standard definition table. Tester can use this table to extract the error from tester and signal path. These calibration elements can be designed as size as DUT for on production line auto calibration.

After finishing SOLT calibration, the error form tester and signal path can be modified. In this way, tester can measure the performance of DUT directly. This testing interface not only can make socket design much easier, but also can measure the performance of DUT precisely.

Pang Cheng Chiu
Pang Cheng Chiu received the B.S. degree in Electronic Communication Engineering from National Kaohsiung Marine University, Taiwan, in 2008. Now is studying the M.S. in Electronic Engineering in National University of Kaohsiung, Taiwan.
Since 2011, joined Accton Technology Corporation, Hsinchu, Taiwan, where was a RF Hardware Engineer. In 2014, joined Jthink Technology, Ltd., who current research interests including signal integrity, power integrity, measurement system for probing and electromagnetic interference designs in high-speed digital systems for packages and printed circuit boards.

Abstract and Biography (Chinese)

传统的高速高频测试插座,根据待测芯片的引脚定义,信号引脚通常被一个或多个接地引脚所包裹。因 此,信号引脚自身的阻抗会受待测芯片的引脚分布限制。例如,一个信号引脚被8个接地引脚所包裹 ,信号引脚的阻抗由待测芯片的引脚间的距离决定.。为解决此问题,Jthink Technology 提出了一种金 属测试插座的设计。测试插座的外壳为金属,信号的传输路径可以被近似看作是一种同轴结构. 因此, 此类引脚间距的金属测试插座对于信号引脚的阻抗匹配将不再是个问题。

从测量的角度来看,TRL校准可以将参考面置于pogo pin与测试板之间。这种方法就是在高频高速半导 体测试时在ATE与DUT之间实现阻抗匹配。

移动校准面到Pogo pin的顶端,将SOLT校准的所需的短路、开路、负载、直通所需的四种标准件制成一 个标准的表格。而后tester可以根据该表格查询tester与信号路径之间的错误。可以将这些校准件的尺寸制作成和待测芯片相仿,并放置于产线上进行自动测量校准。


Pang Cheng Chiu
邱邦誠,於2008年大學畢業於台灣的高雄海洋科技大學 電訊工程系。目前攻讀於台灣的 高雄大學 電機工程系 碩士學歷中。
從2011年,至智邦科技有限公司 擔任 射頻工程師。主要工作內容為 WiFi 產品開發。而 2014 年中 加入目前公司 佳思科技有限公司,目前主要研究及工作內容為 信號整合, 電源 整合, 高頻電磁模擬,高頻探針量測系統開發以及高頻高速系統應用之封裝及電路板設 計。

Link to Session 1 Paper 4
12:15 - 14:00
Lunch &
opens at 13:00
Enjoy the delicious hot buffet lunch and networking time. Then take the time to explore the BiTS EXPO. There will be many great exhibits to explore what is Now & Next in the test and burn-in of semiconductors. You will be certain to see something new or meet someone new.

As attendees to BiTS know, there is always excellent food, drinks, and time for attendees to network with exhibitors!

BiTS EXPO will open at 13:00 and will remain open throughout the afternoon until 18:00

14:00 - 16:00
Session 2
Socket Technology
Latest presentations on sockets, probe pins, and elastomers.
Hear up-to-date local presentations from across Asia describing semiconductor test and burn-in challenges. These regional and global experts will share their expertise and solutions to these challenges.

Technical presentations in Chinese or English as noted. Slides in English with bilingual question & answer period.

"Study of Probe Pin Internal Resistance"
Ribbon for best Paper
Takuto Yoshida
Test Tooling Solutions Group
Abstract and Biography (English)

It is very important to keep a low constant resistance in the design of the probe pin. All the pin parts design has a big influence on the resistance. The design of parts shape, base material, plating, surface roughness, spring force and etc. has impact to contact resistance. The resistance value of the metal is simple to calculate. However it's difficult to get accurate value for the contact resistance of metal and metal by calculation. Usually more than 3 locations of the contact portion exist in the probe pin. (Between Device pad and Plunger A, Plunger and barrel and Plunger B and PCB pad)

We actually measure the resistance of the probe pin, we can actually measure only the resistance value between the PA side and the PB-side pad. All of the contact resistance values are buried in the whole of the resistance value.

I will introduce the results of a challenge to actually measure the contact resistance between the parts that make up the probe pins using a jig in this lecture. As a result, the contact resistance of which part is dominant for the entire pin. I was able to get the indicators such as how and the design or lower resistance pin can be. Further, by measuring the probe pin after the durability test, and identify which contact resistance value at the portion is increased, it could prove to be able to also assist in the high durable probe pin design.

Takuto Yoshida
Yoshida-san earned his Bachelor of Engineering from The University of Electro- Communications, Japan in 1984. He joined Test Tooling Solutions Group in 2011 where he is the Technology Manager responsible for path finding, test and validation. Yoshida-san is a member of the BiTS China Technical Program committee.

Abstract and Biography (Chinese)

保持低而稳定的电阻值对弹簧探针的设计至关重要。弹簧探针所有零件的设计都对阻值有很大的 影响。零件的外形、基材、电镀、表面粗糙度、弹簧力等等都会影响接触电阻。金属材料的阻 值容易计算。然而,计算出金属与金属之间,精确的接触电阻會比较困难。 通常在弹簧探针中,會有三个以上的接触点。(芯片触点和上测试针头之间,测试针头和套管 之间,以及下测试针头和电路板触点之间)

我们可以测量弹簧探针的阻值, 也可以只测量上测试针端和下测试针端之间的整体阻值。 整体的阻值會涵蓋所有的内部接触电阻。

这次演讲我将要介绍,如何通过一台治具,准确测量出弹簧探针零件之间的阻值以及该设计的难点。从而得到结论,哪部分的接触电阻对整个弹簧探针的电阻才是具有决定性作用的。过程中,我还得到了一些 关键指标,例如,如此设计的低阻值弹簧探针的下限何在。此外,探针经过耐久测试后,可以測 量出哪一部分的接触电阻增加了,这也有助于我们设计出更高寿命的弹簧探针。

Takuto Yoshida
Yoshida在1984年畢業於日本電氣通信大學, 获得了工程学士学位。2011年,他以 技術研發經理的身份, 加入Test Tooling Solutions Group,主要负责新产品研发、测 试和验证。Yoshida目前是BiTS China Technical Program委员会成员。

Link to Session 2 Paper 1

"Monte Carlo Analysis for PoP Alignment"
DeXian (Frank) Liu
Smiths Connectors
Resty Querubin
Smiths Connectors
Siang Soh
Smiths Connectors
Abstract and Biography (English)

Technology is accelerating at an unbelievably quick pace and size matters! Mobile communication devices such as smart phones and PDA’s keep getting smarter, while requiring increasingly smaller packaging. These requirements have led to the development of innovative packaging methodologies such as Package-on- Package (PoP) devices that offer the capability of increasing processor and memory chip connections.

Early in PoP package development, 0.50 mm pitch was the goal for I/O spacing. Today, 0.20-0.40 mm pitch is difficult, but achievable, for the package manufacturer. However, this proves a major challenge for test socket designers to develop a robust PoP test contactor solution which validates that the PoP package is working properly.

No longer can test socket developers rely solely on Worst Case or Root Sum Square tolerance analyses to optimize their socket designs. Small pad features on PoP packages prove to be a moving target for test probes to contact. Alignment optimization using Monte Carlo tolerance analysis is critical to success. Successfully recognized for several years, Monte Carlo tolerance analysis is a proven tool using predictive statistical methods by developing a model of known design parameters and optimizing manufacturing processes in order to improve alignment repeatability and enhance design performance. This is especially critical in developing a robust PoP test contactor solution that keeps pace with rapidly reducing pitch requirements, <0.25 mm.

In this presentation, we will discuss a typical MC analysis that can be performed on several basic PoP test socket applications including memory-less and memory bearing design configurations. Through MC analysis we can also perform spring probe and socket design optimization based on different package solder ball / pad geometries.

The results of this study will demonstrate how MC analysis can be used to perform spring probe to solder ball / pad alignment analysis based on different package designs, geometries, and tolerances in order to optimize socket design. This eliminates the cost of developing multiple test vehicles and further highlights the need for package tolerance improvements.

Frank Liu
Frank Liu graduated from Shandong University of Science and Technology in 2001, his major is Mechanical designer. He has joined in Smith Connector over 9 years. Now he worked as a Sr designer engineer and a team leader leading the new product development in semi group. He was one of author for several BiTS papers, “Signal Integrity & Impacts by Connector Structures” in BiTS China 2015, “IM Material for High Pin Count Socket” in BiTS 2012.

Abstract and Biography (Chinese)

技术发展日新月异,尺寸大小至关重要!移动通讯设备如智能手机和 PDA越来越智能,同时对更小尺寸的芯片封装也需求越来越多。这些需求也促进了创新 型的封装技术发展,例如PoP封装技术,有效改善了处理器芯片和存储器芯片之间的连接。

PoP封装技术早期发展阶段的I/O引脚间距的目标是0.50毫米。今天,对芯片封 装供应商来说,0.20-0.40mm的I/O引脚间距虽难,但是也已经可以实现。但如此小的引脚设计也给芯片测试座的研发带来新挑战,如何开发出可靠的PoP芯片测试座来验证PoP芯 片是否工作正常?

测试座的开发人员已经不单纯的依赖于极值分析法或者平方公差法。小的接触 引脚往往会导致弹簧探针接触不良。采用蒙特卡洛分析法进行优化分析有助于解决问 题。经过多年使用,蒙特卡洛分析法已经被证明是非常有用的工具,它是一种统计 学预测的方法,可以通过设计参数建立数学模型并通过优化加工工艺进而提高定位的可重 复性、保证设计的性能要求。特别是针对PoP芯片的引脚间距进一步缩小的芯片测试(小 于0.25mm),开发出更可靠的PoP测试座来说,尤为重要。

这篇演讲稿,我们主要讨论蒙特卡洛分析法应用在PoP芯片测试座,包含 Memory-less和Memory Bearing两种设计结构。通过蒙特卡洛分析,我们也可以针对不 同的锡球/焊盘的形状对弹簧探针和测试座进行优化分析。

研究结果将会阐述如何通过蒙特卡洛分析法、基于不同的封装设计、外形尺寸 、公差要求,对弹簧探针和锡球/焊盘的定位进行分析,进而优化测试座的设计。不仅消除了为开发各种验证工具而产生的成本,而且进一步凸显了封装尺寸公差改善 的需求。

Frank Liu
刘德先(Frank Liu)于2001年毕业于山东科技大学,机械专业。已经在SMITHS CONNETORS超过9年。目前他作为一个资深研发工程师和团队主管主要负责新产 品开发。他是好几篇Bits文章的作者之一。如: 2015年Bits中国,《芯片测试探针/ 座结构对信号完整性的影响》,2012年, 《IM材料应用在多引脚的测试座》。

Link to Session 2 Paper 2

"Conductive Elastomer vs Spring Probe: Performance & Application"
Jiachun (Frank) Zhou
Smiths Connectors
Abstract and Biography (English)

Conductive elastomer contactors have been applied in IC package testing for many years. The elastomer contactors on the market have common structures using elastomer sheets populated with conductive elements, such as Ni, Ag, or Au particles or Cu wire with Au plating. With their specific structures and characteristics, conductive elastomers have their own contact behaviors. Another major contact technology, spring probes (pogo pin) have been extensively applied in IC package testing over 30 years. Most IC package test professionals are very familiar with spring probe structures and their contact characteristics. Knowing the characteristics of these two contactor technologies will ensure the proper selection of contactors for every specific IC package testing application.

As well known, the compression travel of a spring probe comes from the spring in the barrel. The compression distance and force of a spring probe follows a linear equation with a spring constant predicting the force at a compression length. Other components’ structures, such as plungers, have little impact on spring behavior although the barrel’s internal surface smoothness and gap between barrel ID and spring OD have minimal impacts on spring force. The compression travel of a conductive elastomer comes from squeezing the elastomer. Elastomers behave like high density fluid under external force compression. It generates mechanical resistance or force again external compression and recovers when the external force disappears. As with a fluid, the correlation between force and compression may not be linear or only partially linear. More important, the structure of external components, have a big effect on the correlation of force and travel. For example, the surface feature of the external contactor, such as a plunger, can generate very high force if its surface is flat.

Cleaning spring probes is a common practice on an IC package testing floor. It can be cleaned with brush, IPA, Acetone, Laser, solid CO2, etc. One limitation of conductive elastomers is contamination on the conductive column surface if there is direct contact between the package ball and elastomer. The solder particles from BGA balls stuck on the elastomer contactor surface may cause high resistance. One solution in a conductive elastomer application is to place a contact sheet above the elastomer. The contact sheet will maintain reliable contact between the device and elastomer and also be easily cleaned. It extends the usage life of elastomer.

This paper will compare the differences between spring probes and conductive elastomers in structure, performance, strengths and weaknesses, as well cleaning methodologies to help understanding their characteristics, particularly those of conductive elastomers.

Jiachun Zhou (Frank), PhD
Frank Zhou has been working in Semiconductor test equipment and contactor industry over 16 years with focus on new technologies and products development. He is major contributor on various new spring probe and test socket technologies. Frank graduated from University of Hawaii with Mechanical & Material Engineering PhD in 1998. He is now working in Smiths Connectors as Technical Fellow and Engineering Director. He has over 20 patents in spring probes and test sockets and over 50 publications in journals and international conferences.

Abstract and Biography (Chinese)

采用导电胶制作的芯片测试座已经应用在半导体芯片测试领域许多年。导电胶测试座基本 结构是采用橡胶薄片,内部植入导电元件,如镍、银、金颗粒或者镀金的铜线。基于它的这种结 构和特点,导电胶具有独特的电学性能表现。另外一种主要测试技术,弹簧探针已经广泛应用于 半导体芯片测试领域30年以上。半导体测试行业领域的专家对弹簧探针的结构和性能都非常熟悉。 了解这2种技术的特点有利于帮助我们根据不同的芯片及测试要求选择合适的测试技术及测试座。

众所周知,弹簧探针的压缩行程主要来自于套管(Barrel)内弹簧。压缩行程和弹力符合线 性方程,可以通过弹簧的弹性系数来预测出在规定的压缩行程内所能获得的弹力。其他的零件结 构,套管(Barrel)的内壁光洁度、接触针(Plungers)以及弹簧的外径与套管(Barrel)内壁的摩 擦对弹簧的弹力影响微乎其微。弹性胶的行程主要来自于橡胶的挤压回弹。它的变形类似于高密 度的流体在受到外部压力的时候,流体内部产生出阻力以抵抗外力,当外力消失时,恢复为原始 状态。流体的压缩和弹力的关系往往不是线性的或者只有部分线性关系。更重要的是,其他部件 的结构对弹力和行程的关系影响较大。例如:如果外部接触面是面积较大,弹性橡胶将产生更大 的弹力。

清洁方法:芯片测试车间对弹性探针的清洗都非常熟悉。可以采用毛刷清洁,异丙醇或丙 酮超声波清洁,激光清洁,固态二氧化氮清洁等等。对导电橡胶技术的一个主要限制是,如果芯 片的测试球和导电橡胶直接接触,BGA芯片的锡球残渣或一些污染物很容易堆积到导电橡胶棒上 造成高阻值。一个解决方案就是在导电橡胶上放置一个接触头组片(Contact Sheet)。这个接触 头组片(Contact Sheet)能确保芯片和导电橡胶的良好接触,易于清洁并延长导电橡胶的寿命。

这篇论文主要比较弹性探针技术和导电胶技术在结构上,性能表现上,优点和缺点,以及 清洁方法来帮助了解它们各自的特点,特别是导电胶技术。

Jiachun Zhou (Frank), PhD
Frank Zhou 在半导体测试设备与连接器行业拥有超过 16年的专业经验,负责新连接 器技术与产品的研发,是多个新探针和测试 socket 技术的发明人。他在Smiths Connectors作为研究员和技术总监负责管理全球半导体连接器 产品 设计和研发工程部。他在半导体连接器领域拥有 20 项与产品及技术相关的专利,并在行业期刊及国际 会议上发表超过 50 篇论文。Frank 1998 年毕业于夏威夷大学,拥有机械工程与材料科学 博士学位。

Link to Session 2 Paper 3

"Do Socket and Kits Design Matter for Die Cracking?"
Yuanjun Shi
Twin Solution Technology
Kane Liu
Twin Solution Technology
Abstract and Biography (English)

For FT stage, it is easily to detect die crack. Usually, it is very important to understand die crack possible reasons before we design socket and other relevant device. But most socket vendor always focus on socket design, Kits vendor also focus on Kit design, they don’t provide a total solution to test services vender. As we know, socket design will impact on Kits design, correspondingly Kits design also impact on socket test performance. It is very important to know these two technologies can provide the proper test scheme to test services vendor.

This paper will focus on these two aspects to discuss, use FEA tool to simulate die ideal stress state, predict the die easily cracking area, and preliminary determine the hander max pressure. Compare with different design how to impact die stress state, we can try to optimize socket or Kits design. Then repeat simulation and minimize the die surface force stress to prevent die crack. Thus it has become possible to prevent die crack.

Yuanjun Shi

Yuanjun Shi is currently R&D manager of Twinsolution Technology Shanghai INC., He has Bachelor Degree of electronic engineering from Suzhou University and MBA from Victoria University Switzerland. Yuanjun has over 15 years’ experience in the semiconductor industry. Now Yuan Jun’s major focus is on developing high quality metal contactors.

Abstract and Biography (Chinese)

在FT测试阶段,非常容易发生芯片开裂。 在我们设计Socket和相关的测试设备时,对于理 解芯片开裂的原因就显得很重要。 但是大多数的Socket供应商只专注于Socket的设计,而Kits 供应商同样只专注于Kits的设计, 通常不能提供一套完整的测试方案给芯片测试商。 众所周知 ,Socket的设计会影响Kits, Kits的设计同样也会影响Socket的测试性能。能从这两方面提供一 套合适的方案给测试商就显得非常重要。

这篇文章将专注于这两方面的讨论,运用FEA的工具模拟芯片测试的受力情况,预测芯片比 较容易开裂的区域,初步确定Hander的最大压力。比较不同的设计,对应不同芯片受力, 尝试 优化Socket和Kits的设计。 经过反复的仿真分析,让芯片表面的受力达到最小。这样就有可能 预防芯片的开裂。

Yuanjun Shi

施 元军目前是上 海韬盛电子科技股份有限公司的研发经理。他在半导体测试产业有超过15年 的经验,并致力于测试连接器对信号和电源完整性影响研究多年。他还多次提交并获得专利,其中以高 隔离度的测试插座的研发最具代表性。目前他主要专注于开发低接触电阻和长寿命的金属接触探针。

Link to Session 2 Paper 4
16:00 - 18:00
& Afternoon Tea
BiTS EXPO Continues
Enjoy additional time to meet with the presenters, network, and explore the BiTS EXPO further. There will be many great exhibits to explore what is Now & Next in the test and burn-in of semiconductors.

Afternoon refreshments will be served.

Program subject to change without notice.
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